Design and Optimization of 4-BIT Static RAM and 4-BIT Dynamic RAM for Compact and Portable Devices
DOI:
https://doi.org/10.56532/mjsat.v1i3.19Keywords:
SRAM, DRAM, Leakage Power, Sleepy StackAbstract
As technology advances, the combined compactness of transistors also increases. Portable electronics such as cellphones, notebooks, and laptops are in high demand. The enhanced innovation reduces the feature value for this compact design. Devices with a small feature set require less electricity to operate. The edge voltage is reduced when the power source is reduced. Low-limit devices perform better, but in such a deep submicron domain, sub-edge leakage current is critical. As a result, architects should focus on decreasing leakage. Several field workers have presented divergent ideas to explain this. A 4-bit static RAM cell using the reduction of the leakage power consumption (sleepy stack) technique and the 4-bit DRAM is proposed in this paper. The RAMs' schematic was produced using DSCH, and their layout was built using MICROWIND. Improved power consumption in static random-access memory by combining a sleepy stack with a keeper strategy and constructing a 4-bit dynamic random-access memory was explained as a result of this research. According to the findings, the higher the technology used, the higher the power consumption. On the other hand, after assessing the results, SRAM uses less electricity and has more transistors per memory.
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