Design and FPGA Implementation of a 32-Bit Single-Cycle RISC-V Processor

Abstract

The Reduced Instruction Set Computer Five (RISC-V) instruction set architecture (ISA) is open-source and has become increasingly prominent in computer architecture education due to its flexibility and accessibility. However, most educational implementations rely primarily on simulation, with limited emphasis on hardware validation. This paper presents the design, implementation and hardware validation of a 32-bit single-cycle RISC-V processor based on the RV32I instruction set. The processor was developed in Verilog HDL with a complete integration of datapath and control unit. Functional verification was first performed in ModelSim-Altera using six instruction categories, followed by synthesis and deployment on a Terasic DE1-SoC FPGA Development board using Intel Quartus Prime Lite. A total of 31 RV32I instructions were successfully implemented and verified through simulation, while 29 instructions were further validated on the Field-Programmable Gate Array (FPGA) using five representative applications, including a password lock system and a temperature-controlled fan controller. The implementation utilized only 17% of the FPGA logic elements, achieved a maximum operating frequency of 53.31 MHz and consumed 422.07 mW of power. These results confirm the functional correctness and hardware efficiency of the designed processor, demonstrating FPGA-based RISC-V development as a practical platform for bridging the gap between simulation-based learning and hands-on processor architecture education.